A 65 nm Sub-t microcontroller with integrated SRAM and switched capacitor DC-DC converter

Joyce Kwong, Yogesh K. Ramadass, Naveen Verma, Anantha P. Chandrakasan

Research output: Contribution to journalArticlepeer-review

186 Scopus citations

Abstract

Aggressive supply voltage scaling to below the device threshold voltage provides significant energy and leakage power reduction in logic and SRAM circuits. Consequently, it is a compelling strategy for energy-constrained systems with relaxed performance requirements. However, effects of process variation become more prominent at low voltages, particularly in deeply scaled technologies. This paper presents a 65 nm system-on-a-chip which demonstrates techniques to mitigate variation, enabling sub-threshold operation down to 300 mV. A 16-bit microcontroller core is designed with a custom sub-threshold cell library and timing methodology to address output voltage failures and propagation delays in logic gates. A 128 kb SRAM employs an 8 T bit-cell to ensure read stability, and peripheral assist circuitry to allow sub-$V-{t}$ reading and writing. The logic and SRAM function in the range of 300 mV to 600 mV, consume 27.2 pJ/cycle at the optimal $V- DD}$ of 500 mV, and 1 $μ{W}}$ standby power at 300 mV. To supply variable voltages at these low power levels, a switched capacitor DC-DC converter is integrated on-chip and achieves above 75% efficiency while delivering between 10 $μ{W}}$ to 250 $μ{W}}$ of load power.

Original languageEnglish (US)
Article number4735556
Pages (from-to)115-126
Number of pages12
JournalIEEE Journal of Solid-State Circuits
Volume44
Issue number1
DOIs
StatePublished - Jan 1 2009
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Keywords

  • CMOS digital integrated circuits
  • DC-DC conversion
  • Leakage currents
  • Logic design
  • Low-power electronics
  • SRAM
  • Subthreshold

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