A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS

Amit Kumar, Partha Kundu, Arvind P. Singh, Li Shiuan Peh, Niraj Kumar Jha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

204 Scopus citations

Abstract

As chip multiprocessors (CMPs) become the only viable way to scale up and utilize the abundant transistors made available in current microprocessors, the design of on-chip networks is becoming critically important. These networks face unique design constraints and are required to provide extremely fast and high bandwidth communication, yet meet tight power and area budgets. In this paper, we present a detailed design of our on-chip network router targeted at a 36-core shared-memory CMP system in 65nm technology. Our design targets an aggressive clock frequency of 3.6GHz, thus posing tough design challenges that led to several unique circuit and microarchitectural innovations and design choices, including a novel high throughput and low latency switch allocation mechanism, a non-speculative single-cycle router pipeline which uses advanced bundles to remove control setup overhead, a low-complexity virtual channel allocator and a dynamically-managed shared buffer design which uses prefetching to minimize critical path delay. Our router takes up 1.19 mm 2 area and expends 551 mW power at 10% activity, delivering a single-cycle no-load latency at 3.6GHz clock frequency while achieving a peak switching data rate in excess of 4.6Tbits/sper router node.

Original languageEnglish (US)
Title of host publication2007 IEEE International Conference on Computer Design, ICCD 2007
Pages63-70
Number of pages8
DOIs
StatePublished - Dec 1 2007
Event2007 IEEE International Conference on Computer Design, ICCD 2007 - Lake Tahoe, CA, United States
Duration: Oct 7 2007Oct 10 2007

Publication series

Name2007 IEEE International Conference on Computer Design, ICCD 2007

Other

Other2007 IEEE International Conference on Computer Design, ICCD 2007
CountryUnited States
CityLake Tahoe, CA
Period10/7/0710/10/07

All Science Journal Classification (ASJC) codes

  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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    Kumar, A., Kundu, P., Singh, A. P., Peh, L. S., & Jha, N. K. (2007). A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS. In 2007 IEEE International Conference on Computer Design, ICCD 2007 (pp. 63-70). [4601881] (2007 IEEE International Conference on Computer Design, ICCD 2007). https://doi.org/10.1109/ICCD.2007.4601881