TY - GEN
T1 - A 45nm 0.5V 8T column-interleaved SRAM with on-chip reference selection loop for sense-amplifier
AU - Sinangil, Mahmut E.
AU - Verma, Naveen
AU - Chandrakasan, Anantha P.
N1 - Copyright:
Copyright 2010 Elsevier B.V., All rights reserved.
PY - 2009
Y1 - 2009
N2 - 8T bit-cells hold great promise for overcoming device variability In deeply scaled SRAMs and enabling aggressive voltage scaling for ultra-low-power. This paper presents an array architecture and circuits with minimal area overhead to allow column-interleaving while eliminating the half-select problem. This enables sense-amplifier sharing and soft-error Immunity. A reference selection loop is designed and implemented in the column circuitry. By choosing one of the two reference voltages for each sense-amplifier in a pseudo-differential scheme, selection loop effectively reduces input offset. 8T test array fabricated in 45nm CMOS achieves functionality from 1.1V to below 0.5V. Test chip operates at 450MHz at 1.1V and 5.8MHz at 0.5V while consuming 12.9mW and 46μW respectively.
AB - 8T bit-cells hold great promise for overcoming device variability In deeply scaled SRAMs and enabling aggressive voltage scaling for ultra-low-power. This paper presents an array architecture and circuits with minimal area overhead to allow column-interleaving while eliminating the half-select problem. This enables sense-amplifier sharing and soft-error Immunity. A reference selection loop is designed and implemented in the column circuitry. By choosing one of the two reference voltages for each sense-amplifier in a pseudo-differential scheme, selection loop effectively reduces input offset. 8T test array fabricated in 45nm CMOS achieves functionality from 1.1V to below 0.5V. Test chip operates at 450MHz at 1.1V and 5.8MHz at 0.5V while consuming 12.9mW and 46μW respectively.
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U2 - 10.1109/ASSCC.2009.5357219
DO - 10.1109/ASSCC.2009.5357219
M3 - Conference contribution
AN - SCOPUS:76249108649
SN - 9781424444342
T3 - Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
SP - 225
EP - 228
BT - Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
T2 - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
Y2 - 16 November 2009 through 18 November 2009
ER -