A 45nm 0.5V 8T column-interleaved SRAM with on-chip reference selection loop for sense-amplifier

Mahmut E. Sinangil, Naveen Verma, Anantha P. Chandrakasan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

21 Scopus citations

Abstract

8T bit-cells hold great promise for overcoming device variability In deeply scaled SRAMs and enabling aggressive voltage scaling for ultra-low-power. This paper presents an array architecture and circuits with minimal area overhead to allow column-interleaving while eliminating the half-select problem. This enables sense-amplifier sharing and soft-error Immunity. A reference selection loop is designed and implemented in the column circuitry. By choosing one of the two reference voltages for each sense-amplifier in a pseudo-differential scheme, selection loop effectively reduces input offset. 8T test array fabricated in 45nm CMOS achieves functionality from 1.1V to below 0.5V. Test chip operates at 450MHz at 1.1V and 5.8MHz at 0.5V while consuming 12.9mW and 46μW respectively.

Original languageEnglish (US)
Title of host publicationProceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
Pages225-228
Number of pages4
DOIs
StatePublished - 2009
Externally publishedYes
Event2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009 - Taipei, Taiwan, Province of China
Duration: Nov 16 2009Nov 18 2009

Publication series

NameProceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009

Other

Other2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
Country/TerritoryTaiwan, Province of China
CityTaipei
Period11/16/0911/18/09

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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