A 45nm 0.5V 8T column-interleaved SRAM with on-chip reference selection loop for sense-amplifier

Mahmut E. Sinangil; Naveen Verma; Anantha P. Chandrakasan

doi:10.1109/ASSCC.2009.5357219

A 45nm 0.5V 8T column-interleaved SRAM with on-chip reference selection loop for sense-amplifier

Mahmut E. Sinangil, Naveen Verma, Anantha P. Chandrakasan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

21 Scopus citations

Abstract

8T bit-cells hold great promise for overcoming device variability In deeply scaled SRAMs and enabling aggressive voltage scaling for ultra-low-power. This paper presents an array architecture and circuits with minimal area overhead to allow column-interleaving while eliminating the half-select problem. This enables sense-amplifier sharing and soft-error Immunity. A reference selection loop is designed and implemented in the column circuitry. By choosing one of the two reference voltages for each sense-amplifier in a pseudo-differential scheme, selection loop effectively reduces input offset. 8T test array fabricated in 45nm CMOS achieves functionality from 1.1V to below 0.5V. Test chip operates at 450MHz at 1.1V and 5.8MHz at 0.5V while consuming 12.9mW and 46μW respectively.

Original language	English (US)
Title of host publication	Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
Pages	225-228
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2009.5357219
State	Published - 2009
Externally published	Yes
Event	2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009 - Taipei, Taiwan, Province of China Duration: Nov 16 2009 → Nov 18 2009

Publication series

Name	Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009

Other

Other	2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
Country/Territory	Taiwan, Province of China
City	Taipei
Period	11/16/09 → 11/18/09

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ASSCC.2009.5357219

Cite this

Sinangil, M. E., Verma, N., & Chandrakasan, A. P. (2009). A 45nm 0.5V 8T column-interleaved SRAM with on-chip reference selection loop for sense-amplifier. In Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009 (pp. 225-228). [5357219] (Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009). https://doi.org/10.1109/ASSCC.2009.5357219

Sinangil, Mahmut E. ; Verma, Naveen ; Chandrakasan, Anantha P. / A 45nm 0.5V 8T column-interleaved SRAM with on-chip reference selection loop for sense-amplifier. Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009. 2009. pp. 225-228 (Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009).

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abstract = "8T bit-cells hold great promise for overcoming device variability In deeply scaled SRAMs and enabling aggressive voltage scaling for ultra-low-power. This paper presents an array architecture and circuits with minimal area overhead to allow column-interleaving while eliminating the half-select problem. This enables sense-amplifier sharing and soft-error Immunity. A reference selection loop is designed and implemented in the column circuitry. By choosing one of the two reference voltages for each sense-amplifier in a pseudo-differential scheme, selection loop effectively reduces input offset. 8T test array fabricated in 45nm CMOS achieves functionality from 1.1V to below 0.5V. Test chip operates at 450MHz at 1.1V and 5.8MHz at 0.5V while consuming 12.9mW and 46μW respectively.",

author = "Sinangil, {Mahmut E.} and Naveen Verma and Chandrakasan, {Anantha P.}",

year = "2009",

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language = "English (US)",

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Sinangil, ME, Verma, N & Chandrakasan, AP 2009, A 45nm 0.5V 8T column-interleaved SRAM with on-chip reference selection loop for sense-amplifier. in Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009., 5357219, Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009, pp. 225-228, 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009, Taipei, Taiwan, Province of China, 11/16/09. https://doi.org/10.1109/ASSCC.2009.5357219

A 45nm 0.5V 8T column-interleaved SRAM with on-chip reference selection loop for sense-amplifier. / Sinangil, Mahmut E.; Verma, Naveen; Chandrakasan, Anantha P.
Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009. 2009. p. 225-228 5357219 (Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Sinangil ME, Verma N, Chandrakasan AP. A 45nm 0.5V 8T column-interleaved SRAM with on-chip reference selection loop for sense-amplifier. In Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009. 2009. p. 225-228. 5357219. (Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009). doi: 10.1109/ASSCC.2009.5357219

A 45nm 0.5V 8T column-interleaved SRAM with on-chip reference selection loop for sense-amplifier

Abstract

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