A 32kB secure cache memory with dynamic replacement mapping in 65nm bulk CMOS

Burak Erbagci, Fangfei Liu, Cagla Cakir, Nail Etkin Can Akkaya, Ruby Bei-Loh Lee, Ken Mai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Side channel attacks exploit inadvertent information leakage from the physical implementation of computing systems, bypassing the theoretical strength of cryptographic algorithms. Of particular concern are software side-channel attacks which can be mounted remotely without access or alteration of the hardware system. One type of attack that has been demonstrated to be highly effective is cache timing attacks that exploit cache replacement policies to discern information about the data being processed. In this paper, we present a secure cache design that defeats software side-channel attacks targeted at hardware caches. The memory-to-cache mapping is dynamic and randomized by replacing the address decoder of a conventional cache with a CAM. We fabricated a prototype 32kB secure cache along with a conventional 8-way version for comparison on a 65nm bulk CMOS process. The prototype operates at 500 MHz, dissipating 117 mW at the nominal 1V VDD. Compared to the conventional design, the secure cache has an 10% area overhead, 20% power overhead at iso-performance.

Original languageEnglish (US)
Title of host publication2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467371919
DOIs
StatePublished - Jan 19 2016
Event11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Xiamen, Fujian, China
Duration: Nov 9 2015Nov 11 2015

Publication series

Name2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings

Other

Other11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015
CountryChina
CityXiamen, Fujian
Period11/9/1511/11/15

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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    Erbagci, B., Liu, F., Cakir, C., Akkaya, N. E. C., Lee, R. B-L., & Mai, K. (2016). A 32kB secure cache memory with dynamic replacement mapping in 65nm bulk CMOS. In 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings [7387501] (2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASSCC.2015.7387501