A 3-D CPU-FPGA-DRAM Hybrid Architecture for Low-Power Computation

Keyphrases

• Hybrid Architecture 100%
• Field Programmable Gate Array 100%
• Low Computation Power 100%
• Power Delay Product 50%
• Power Budget 50%
• Power Reduction 50%
• 3D IC 50%
• Dark Silicon 50%
• Low Power 25%
• High Performance 25%
• Proposed Architecture 25%
• Technology Node 25%
• Level of Functioning 25%
• Letting 25%
• Two-layer 25%
• Moore's Law 25%
• Data Cache 25%
• Multiple Cores 25%
• System Designer 25%
• Out-of-order 25%
• L3 Cache 25%
• Utilization Wall 25%
• Major Challenges 25%
• Transistor 25%
• Communication Mode 25%
• Fast Switching 25%

Computer Science

• Hybrid Architecture 100%
• Field Programmable Gate Array 100%
• Energy Delay Product 50%
• Integrated Circuit 50%
• Application Level 25%
• Moore's Law 25%
• System Designer 25%
• Reduce Function 25%
• Transistor 25%

Mathematics

• Low Power 100%
• Reduce Function 50%