This paper presents a 256-kb in-memory computing (IMC) macro implemented in 22nm CMOS with foundry MRAM. IMC leverages high levels of parallelism (both rows/columns within macro and multiple macros across chip), but where previous architectures have not addressed the data-dependent interference/noise between highly sensitive parallel analog circuits. Here, an IMC macro with differential readout architecture is demonstrated, which retains high energy efficiency, while overcoming the power-supply interference between the many parallel readout channels. High-sensitivity conductance-to-current readout is demonstrated, without relying on non-standard foundry cells, having atypical cell-state resistances or non-standard array configurations, and without relying on reduced row/column parallelism. The macro achieves state-of-the-art energy efficiency of 28.0-68.6 lb-TOPS/W and compute density of 5.43 1b-TOPS/mm2. CIFAR-10 classification is demonstrated, achieving software iso-accuracy of 90.25%, with all convolutional layers mapped to the chip.