A 10-b statistical ADC employing pipelining and sub-ranging in 32nm CMOS

Sen Tao; Naveen Verma; Ryan M. Corey; Andrew C. Singer

doi:10.1109/ISCAS.2017.8050245

A 10-b statistical ADC employing pipelining and sub-ranging in 32nm CMOS

Sen Tao, Naveen Verma, Ryan M. Corey, Andrew C. Singer

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

This paper presents a 10-b statistical ADC (S-ADC), achieving higher resolution (INL) than any previously reported S-ADC. This resolution requires a large number of statistical observations via comparators (12k) with offset variation, making code estimation a key challenge. The efficiency of estimation is enhanced by a coarse frontend estimator, employing pipelining and sub-ranging to arrive at a reduced range, which is then provided to a fine backend estimator. The total computations are reduced by 19×, compared to single-stage estimation over the entire analog range. Implemented in a 32nm process, the S-ADC achieves INL<1.73 LSB and total code estimation error (non-linearity and noise) <2.3 LSBrms. Designed to run at 20MHz, excess supply impedance limits comparator speed to 2MHz. The energy per 10-b conversion for the comparator array (at 2MHz) is 744 pJ and the energy per 10-b conversion of the digital estimator (at 20MHz) is 627 pJ.

Original language	English (US)
Title of host publication	IEEE International Symposium on Circuits and Systems
Subtitle of host publication	From Dreams to Innovation, ISCAS 2017 - Conference Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781467368520
DOIs	https://doi.org/10.1109/ISCAS.2017.8050245
State	Published - Sep 25 2017
Event	50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 - Baltimore, United States Duration: May 28 2017 → May 31 2017

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Other

Other	50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
Country/Territory	United States
City	Baltimore
Period	5/28/17 → 5/31/17

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Keywords

Analog-digital conversion
analog-digital integrated circuits
estimation
statistical distributions

Access to Document

10.1109/ISCAS.2017.8050245

Cite this

Tao, S., Verma, N., Corey, R. M., & Singer, A. C. (2017). A 10-b statistical ADC employing pipelining and sub-ranging in 32nm CMOS. In IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings Article 8050245 (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2017.8050245

Tao, Sen ; Verma, Naveen ; Corey, Ryan M. et al. / A 10-b statistical ADC employing pipelining and sub-ranging in 32nm CMOS. IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. (Proceedings - IEEE International Symposium on Circuits and Systems).

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title = "A 10-b statistical ADC employing pipelining and sub-ranging in 32nm CMOS",

abstract = "This paper presents a 10-b statistical ADC (S-ADC), achieving higher resolution (INL) than any previously reported S-ADC. This resolution requires a large number of statistical observations via comparators (12k) with offset variation, making code estimation a key challenge. The efficiency of estimation is enhanced by a coarse frontend estimator, employing pipelining and sub-ranging to arrive at a reduced range, which is then provided to a fine backend estimator. The total computations are reduced by 19×, compared to single-stage estimation over the entire analog range. Implemented in a 32nm process, the S-ADC achieves INL<1.73 LSB and total code estimation error (non-linearity and noise) <2.3 LSBrms. Designed to run at 20MHz, excess supply impedance limits comparator speed to 2MHz. The energy per 10-b conversion for the comparator array (at 2MHz) is 744 pJ and the energy per 10-b conversion of the digital estimator (at 20MHz) is 627 pJ.",

keywords = "Analog-digital conversion, analog-digital integrated circuits, estimation, statistical distributions",

author = "Sen Tao and Naveen Verma and Corey, {Ryan M.} and Singer, {Andrew C.}",

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doi = "10.1109/ISCAS.2017.8050245",

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Tao, S, Verma, N, Corey, RM & Singer, AC 2017, A 10-b statistical ADC employing pipelining and sub-ranging in 32nm CMOS. in IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings., 8050245, Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers Inc., 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, United States, 5/28/17. https://doi.org/10.1109/ISCAS.2017.8050245

A 10-b statistical ADC employing pipelining and sub-ranging in 32nm CMOS. / Tao, Sen; Verma, Naveen; Corey, Ryan M. et al.
IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. 8050245 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Singer, Andrew C.

PY - 2017/9/25

Y1 - 2017/9/25

N2 - This paper presents a 10-b statistical ADC (S-ADC), achieving higher resolution (INL) than any previously reported S-ADC. This resolution requires a large number of statistical observations via comparators (12k) with offset variation, making code estimation a key challenge. The efficiency of estimation is enhanced by a coarse frontend estimator, employing pipelining and sub-ranging to arrive at a reduced range, which is then provided to a fine backend estimator. The total computations are reduced by 19×, compared to single-stage estimation over the entire analog range. Implemented in a 32nm process, the S-ADC achieves INL<1.73 LSB and total code estimation error (non-linearity and noise) <2.3 LSBrms. Designed to run at 20MHz, excess supply impedance limits comparator speed to 2MHz. The energy per 10-b conversion for the comparator array (at 2MHz) is 744 pJ and the energy per 10-b conversion of the digital estimator (at 20MHz) is 627 pJ.

AB - This paper presents a 10-b statistical ADC (S-ADC), achieving higher resolution (INL) than any previously reported S-ADC. This resolution requires a large number of statistical observations via comparators (12k) with offset variation, making code estimation a key challenge. The efficiency of estimation is enhanced by a coarse frontend estimator, employing pipelining and sub-ranging to arrive at a reduced range, which is then provided to a fine backend estimator. The total computations are reduced by 19×, compared to single-stage estimation over the entire analog range. Implemented in a 32nm process, the S-ADC achieves INL<1.73 LSB and total code estimation error (non-linearity and noise) <2.3 LSBrms. Designed to run at 20MHz, excess supply impedance limits comparator speed to 2MHz. The energy per 10-b conversion for the comparator array (at 2MHz) is 744 pJ and the energy per 10-b conversion of the digital estimator (at 20MHz) is 627 pJ.

KW - Analog-digital conversion

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KW - statistical distributions

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PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017

Y2 - 28 May 2017 through 31 May 2017

ER -

Tao S, Verma N, Corey RM, Singer AC. A 10-b statistical ADC employing pipelining and sub-ranging in 32nm CMOS. In IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc. 2017. 8050245. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS.2017.8050245

A 10-b statistical ADC employing pipelining and sub-ranging in 32nm CMOS

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