A 10-b statistical ADC employing pipelining and sub-ranging in 32nm CMOS

Sen Tao, Naveen Verma, Ryan M. Corey, Andrew C. Singer

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a 10-b statistical ADC (S-ADC), achieving higher resolution (INL) than any previously reported S-ADC. This resolution requires a large number of statistical observations via comparators (12k) with offset variation, making code estimation a key challenge. The efficiency of estimation is enhanced by a coarse frontend estimator, employing pipelining and sub-ranging to arrive at a reduced range, which is then provided to a fine backend estimator. The total computations are reduced by 19×, compared to single-stage estimation over the entire analog range. Implemented in a 32nm process, the S-ADC achieves INL<1.73 LSB and total code estimation error (non-linearity and noise) <2.3 LSBrms. Designed to run at 20MHz, excess supply impedance limits comparator speed to 2MHz. The energy per 10-b conversion for the comparator array (at 2MHz) is 744 pJ and the energy per 10-b conversion of the digital estimator (at 20MHz) is 627 pJ.

Original languageEnglish (US)
Title of host publicationIEEE International Symposium on Circuits and Systems
Subtitle of host publicationFrom Dreams to Innovation, ISCAS 2017 - Conference Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467368520
DOIs
StatePublished - Sep 25 2017
Event50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 - Baltimore, United States
Duration: May 28 2017May 31 2017

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Other

Other50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
CountryUnited States
CityBaltimore
Period5/28/175/31/17

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A 10-b statistical ADC employing pipelining and sub-ranging in 32nm CMOS'. Together they form a unique fingerprint.

  • Cite this

    Tao, S., Verma, N., Corey, R. M., & Singer, A. C. (2017). A 10-b statistical ADC employing pipelining and sub-ranging in 32nm CMOS. In IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings [8050245] (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2017.8050245