This paper presents a 10-b statistical ADC (S-ADC), achieving higher resolution (INL) than any previously reported S-ADC. This resolution requires a large number of statistical observations via comparators (12k) with offset variation, making code estimation a key challenge. The efficiency of estimation is enhanced by a coarse frontend estimator, employing pipelining and sub-ranging to arrive at a reduced range, which is then provided to a fine backend estimator. The total computations are reduced by 19×, compared to single-stage estimation over the entire analog range. Implemented in a 32nm process, the S-ADC achieves INL<1.73 LSB and total code estimation error (non-linearity and noise) <2.3 LSBrms. Designed to run at 20MHz, excess supply impedance limits comparator speed to 2MHz. The energy per 10-b conversion for the comparator array (at 2MHz) is 744 pJ and the energy per 10-b conversion of the digital estimator (at 20MHz) is 627 pJ.