3D vs. 2D device simulation of FinFET logic gates under PVT variations

Keyphrases

• 2D Cross-section 25%
• 2D Device Simulation 100%
• 2D Devices 25%
• 2D Model 50%
• 2D Simulation 25%
• 3D Device Simulation 50%
• 3D Devices 25%
• 3D Model 25%
• 3D Simulation 25%
• Circuit Analysis 25%
• Competitive Edge 25%
• Conventional MOSFET 25%
• CPU Time 50%
• Device Behavior 25%
• Device Model 25%
• Device Yield 25%
• Fin Field-effect Transistor (FinFET) 100%
• Fin Width 25%
• FinFET Devices 25%
• FinFET Technology 25%
• Gate Control 25%
• Gate Length 25%
• Gate Oxide Thickness 25%
• Gate Underlap 25%
• Gate Work Function 25%
• ION-IOFF 25%
• Leakage Current 25%
• Logic Gates 100%
• Mixed-mode Simulation 25%
• MOSFET 25%
• Multigate Structure 50%
• Multigate Transistor 25%
• On-state Current 25%
• Process Variation 100%
• Processing Temperature 100%
• Propagation Delay 25%
• Reduced Susceptibility 25%
• Silicon-on-insulator FinFET 100%
• Simulation Accuracy 25%
• Simulation Efficiency 25%
• Simulation Model 25%
• Single Device 25%
• Subthreshold Leakage Current 25%
• Target Process 25%
• Technology Node 25%
• Temperature Variation 100%
• Voltage Variation 100%

Engineering

• 3d Simulation 25%
• Control Gate 25%
• Cross Section 25%
• Device Behavior 25%
• Electric Network Analysis 25%
• Fin Thickness 25%
• Gate Length 25%
• Gate Oxide 25%
• Logic Gate 100%
• Metal-Oxide-Semiconductor Field-Effect Transistor 50%
• Mixed Mode 25%
• Nodes 25%
• Oxide Thickness 25%
• Process Variation 50%
• Propagation Delay 25%
• Silicon on Insulator 100%
• Simulation Mode 25%
• Single Device 25%
• Transistor 25%

Material Science

• Electronic Circuit 25%
• Metal-Oxide-Semiconductor Field-Effect Transistor 50%
• Oxide Thickness 25%
• Silicon 100%
• Transistor 25%