3D vs. 2D device simulation of FinFET logic gates under PVT variations

Engineering

• Logic Gate 100%
• Silicon on Insulator 100%
• Metal-Oxide-Semiconductor Field-Effect Transistor 50%
• Process Variation 50%
• Nodes 25%
• Cross Section 25%
• Device Behavior 25%
• Mixed Mode 25%
• Control Gate 25%
• Electric Network Analysis 25%
• Oxide Thickness 25%
• Fin Thickness 25%
• Gate Length 25%
• Gate Oxide 25%
• Propagation Delay 25%
• Single Device 25%
• 3d Simulation 25%
• Simulation Mode 25%
• Transistor 25%

Material Science

• Silicon 100%
• Metal-Oxide-Semiconductor Field-Effect Transistor 50%
• Transistor 25%
• Electronic Circuit 25%
• Oxide Thickness 25%

Keyphrases

• Device Model 25%