TY - GEN
T1 - 3D vs. 2D analysis of FinFET logic gates under process variations
AU - Chaudhuri, Sourindra
AU - Jha, Niraj K.
PY - 2011
Y1 - 2011
N2 - Among various multi-gate structures, FinFETs have emerged dominant owing to their ease of fabrication. Thus, characterization of FinFET devices/gates needs immediate attention for them to become the industry driver in this decade. Ideally, 3D device simulation should be done to enable accurate circuit synthesis. However, this is impractical due to the huge CPU times required. Simulating a 2D cross-section of the device yields 100-1000x reduction in CPU time. However, this introduces significant error, in the range of 10% to 50%, while evaluating the on/off current (I ON/I OFF) for a single device and leakage current or propagation delay (I LEAK/t D) for logic gates. In this work, we develop accurate 2D models of FinFET devices to capture 3D simulation accuracy with 2D simulation efficiency. We report results for the 22nm FinFET technology node. As far as we know, this is the first such attempt. We establish the validity of the model even under process variations. We target variations in gate length (L G), workfunction (Φ G) and fin thickness (TSI) that are known to have the most impact on leakage and delay. We adjust their values in the 2D model in order to mimic the actual 3D device behavior. When the 2D models are employed in mixed-mode simulation of FinFET logic gates, the error in the evaluation of I LEAK/t D is quite small.
AB - Among various multi-gate structures, FinFETs have emerged dominant owing to their ease of fabrication. Thus, characterization of FinFET devices/gates needs immediate attention for them to become the industry driver in this decade. Ideally, 3D device simulation should be done to enable accurate circuit synthesis. However, this is impractical due to the huge CPU times required. Simulating a 2D cross-section of the device yields 100-1000x reduction in CPU time. However, this introduces significant error, in the range of 10% to 50%, while evaluating the on/off current (I ON/I OFF) for a single device and leakage current or propagation delay (I LEAK/t D) for logic gates. In this work, we develop accurate 2D models of FinFET devices to capture 3D simulation accuracy with 2D simulation efficiency. We report results for the 22nm FinFET technology node. As far as we know, this is the first such attempt. We establish the validity of the model even under process variations. We target variations in gate length (L G), workfunction (Φ G) and fin thickness (TSI) that are known to have the most impact on leakage and delay. We adjust their values in the 2D model in order to mimic the actual 3D device behavior. When the 2D models are employed in mixed-mode simulation of FinFET logic gates, the error in the evaluation of I LEAK/t D is quite small.
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U2 - 10.1109/ICCD.2011.6081437
DO - 10.1109/ICCD.2011.6081437
M3 - Conference contribution
AN - SCOPUS:83455195319
SN - 9781457719523
T3 - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
SP - 435
EP - 436
BT - 2011 IEEE 29th International Conference on Computer Design, ICCD 2011
T2 - 29th IEEE International Conference on Computer Design 2011, ICCD 2011
Y2 - 9 November 2011 through 12 November 2011
ER -