3-D-TCAD-based parasitic capacitance extraction for emerging multigate devices and circuits

Ajay N. Bhoj, Rajiv V. Joshi, Niraj Kumar Jha

Research output: Contribution to journalArticle

25 Scopus citations

Abstract

In recent years, the multigate field-effect transistor (FET) has emerged as the most viable contender for technology scaling down to the sub-10-nm nodes. The nonplanar nature of multigate devices, along with rapidly shrinking front-end-of-line (FEOL) and back-end-of-line (BEOL) features, has compounded the problem of parasitics extraction in future technology nodes. In this paper, for the first time, we address the above problem through a holistic 3-D-technology CAD (3-D-TCAD) flow for the extraction of FEOL/(FEOL+BEOL) capacitances in generic multigate circuit layouts, using a transport analysis-based approach. We investigate device-level parasitic capacitances in 3-D-process-simulated bulk and silicon-on-insulator FinFETs, and uncover capacitance scaling trends for candidate single/multifin multigate FETs along the 22-nm/14-nm/10-nm technology nodes. Leveraging automated structure synthesis algorithms, we synthesize 3-D multigate 6T SRAM structures using the process-simulated devices, and examine the effects of fin pitch, gate pitch, and fin count on circuit-level parasitics. Thereafter, we show that traditional segregated FEOL/BEOL modeling approaches fail to provide accurate estimates, by back-annotating 3-D-TCAD-extracted capacitances into mixed-mode write simulations of a 6T FinFET SRAM bitcell. Finally, using FinFET NAND2 logic gate delay simulations, we establish the fact that capturing parasitics accurately is as important as modeling device transport accurately, and that performance/dynamic behavior in multigate circuits is highly sensitive to both factors.

Original languageEnglish (US)
Article number6421008
Pages (from-to)2094-2105
Number of pages12
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume21
Issue number11
DOIs
StatePublished - Jan 30 2013

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Keywords

  • Device simulation
  • multigate field-effect transistor (FET)
  • parasitic capacitance
  • process simulation

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