25-nm p-channel vertical MOSFET's with SiGeC source-drains

Min Yang; Chia Lin Chang; Malcolm Carroll; J. C. Sturm

doi:10.1109/55.767105

25-nm p-channel vertical MOSFET's with SiGeC source-drains

Min Yang, Chia Lin Chang, Malcolm Carroll, J. C. Sturm

Research output: Contribution to journal › Article › peer-review

46 Scopus citations

Abstract

The scaling of vertical p-channel MOSFET's with the source and drain doped with boron during low temperature epitaxy is limited by the diffusion of boron during subsequent side wall gate oxidation. By introducing thin SiGeC layers in the source and drain regions, this diffusion has been suppressed, enabling for the first time the scaling of vertical p-channel MOSFET's to under 100 nm in channel length to be realized. Device operation with a channel length down to 25 nm has been achieved.

Original language	English (US)
Pages (from-to)	301-303
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	20
Issue number	6
DOIs	https://doi.org/10.1109/55.767105
State	Published - Jun 1999

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/55.767105

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title = "25-nm p-channel vertical MOSFET's with SiGeC source-drains",

abstract = "The scaling of vertical p-channel MOSFET's with the source and drain doped with boron during low temperature epitaxy is limited by the diffusion of boron during subsequent side wall gate oxidation. By introducing thin SiGeC layers in the source and drain regions, this diffusion has been suppressed, enabling for the first time the scaling of vertical p-channel MOSFET's to under 100 nm in channel length to be realized. Device operation with a channel length down to 25 nm has been achieved.",

author = "Min Yang and Chang, {Chia Lin} and Malcolm Carroll and Sturm, {J. C.}",

note = "Funding Information: Manuscript received July 22, 1998; revised January 7, 1999. This work was supported by Defense Advanced Research Projects Agency, Office of Naval Research, and Air Force Office of Scientific Research. The authors are with the Department of Electrical Engineering, Princeton University, Princeton, NJ 08544 USA. Publisher Item Identifier S 0741-3106(99)05060-0.",

year = "1999",

month = jun,

doi = "10.1109/55.767105",

language = "English (US)",

volume = "20",

pages = "301--303",

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T1 - 25-nm p-channel vertical MOSFET's with SiGeC source-drains

AU - Yang, Min

AU - Chang, Chia Lin

AU - Carroll, Malcolm

AU - Sturm, J. C.

N1 - Funding Information: Manuscript received July 22, 1998; revised January 7, 1999. This work was supported by Defense Advanced Research Projects Agency, Office of Naval Research, and Air Force Office of Scientific Research. The authors are with the Department of Electrical Engineering, Princeton University, Princeton, NJ 08544 USA. Publisher Item Identifier S 0741-3106(99)05060-0.

PY - 1999/6

Y1 - 1999/6

N2 - The scaling of vertical p-channel MOSFET's with the source and drain doped with boron during low temperature epitaxy is limited by the diffusion of boron during subsequent side wall gate oxidation. By introducing thin SiGeC layers in the source and drain regions, this diffusion has been suppressed, enabling for the first time the scaling of vertical p-channel MOSFET's to under 100 nm in channel length to be realized. Device operation with a channel length down to 25 nm has been achieved.

AB - The scaling of vertical p-channel MOSFET's with the source and drain doped with boron during low temperature epitaxy is limited by the diffusion of boron during subsequent side wall gate oxidation. By introducing thin SiGeC layers in the source and drain regions, this diffusion has been suppressed, enabling for the first time the scaling of vertical p-channel MOSFET's to under 100 nm in channel length to be realized. Device operation with a channel length down to 25 nm has been achieved.

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JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 6

ER -

25-nm p-channel vertical MOSFET's with SiGeC source-drains

Abstract

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