Computer Science
Register-Transfer Level
100%
Embedded Systems
92%
Power Consumption
91%
High Level Synthesis
67%
Test Generation
55%
Experimental Result
54%
Control Flow
52%
fault-tolerance
48%
Energy Consumption
47%
Logic Synthesis
39%
Power Management
38%
And Gate
37%
Cellular Automata
32%
Data Controller
31%
Behavioral Description
31%
Synthesis Algorithm
30%
Dynamic Voltage Scaling
29%
Fault Coverage
28%
Power Optimization
28%
Synthesis Tool
26%
Pipelining
26%
Test Application Time
26%
Interconnection Networks
25%
Scheduling Algorithm
25%
Testability Analysis
24%
Task Graph
23%
Dynamic Power
22%
Multiprocessor System
21%
Permanent Fault
21%
Multiplexer
21%
Networks on Chips
20%
Performance Optimization
20%
build-in self-test
20%
Deep Neural Network
20%
Intensive Application
19%
Fault Tolerant
19%
System-on-Chip
19%
Datapath
19%
reconfigurable architecture
19%
Power Dissipation
19%
Concurrent Error Detection
19%
Switching Activity
18%
Single Electron
17%
Embedded Software
17%
Flow Control
17%
Operating Systems
17%
Field Programmable Gate Arrays
17%
Design Automation
16%
Application Specific Integrated Circuit
16%
Chip Multiprocessor
16%
Computer Aided Design
16%
Transient Fault
15%
Energy Efficient
15%
Time Constraint
15%
Power Analysis
14%
Sequential Circuit
14%
Information Symbol
14%
Graphical User Interface
14%
Neural Network
14%
Functional Unit
14%
Generation Time
14%
Combinational Logic
14%
System on a Chip
14%
Machine Learning
14%
System Specification
13%
Automation Tool
13%
Boolean Logic
13%
Memory Architecture
13%
Supply Voltage
13%
Communication Link
13%
Resource Sharing
12%
Control Signal
12%
Distributed Architecture
12%
Floating-Point Operation
12%
Virtual Channel
12%
Speed-up
12%
Sufficient Condition
12%
Processing Element
12%
Network Design
12%
Security protocols
12%
Information Bit
12%
Logic Gate
12%
Building-Blocks
11%
Energy Optimization
11%
Boolean Function
11%
Energy Delay Product
11%
Loop Unrolling
11%
multi-objective evolutionary algorithm
11%
Conditional Branch
11%
Dynamic Behavior
11%
single-chip
11%
Bridging Fault
11%
Real Time Systems
10%
Process Variation
10%
Resource Allocation
10%
Performance Improvement
10%
Regular Expression
10%
Personal Digital Assistant
10%
Security Attack
10%
Dynamic Reconfiguration
10%
Keyphrases
Register Transfer Level
44%
Checkers
40%
High-level Synthesis
37%
Totally Self-checking
36%
Control Flow
36%
CMOS Circuits
36%
Hardware Complexity
35%
Power Consumption
31%
Embedded Systems
27%
Co-synthesis
27%
Behavioral Description
27%
Controller
26%
Algorithm-based Fault Tolerance
26%
Test Case Generation
25%
Fin Field-effect Transistor (FinFET)
25%
Behavioral Synthesis
24%
Area Overhead
20%
Distributed Embedded Systems
19%
Core-Based
19%
Performance Optimization
19%
Testability
19%
Testability Analysis
18%
Stuck-at
18%
Stuck-at Faults
17%
Synthesis Methods
17%
Operating System
16%
Slow Design
16%
Low Overhead
15%
Energy Consumption
14%
Power Optimized
14%
Implantable Devices
14%
Design for Testability
14%
Logic Network
14%
Threshold Logic
14%
Real-time Distributed
14%
Embedded Operating System
14%
Macromodeling
14%
Nanotechnology
14%
Concurrent Error Detection
14%
Power Management
13%
Task Graph
13%
Unidirectional Errors
13%
Self-checking Circuit
13%
Combinational
12%
Application-specific Processors
12%
Communication Link
12%
Resonant Tunneling Diode
12%
Power Optimization
12%
Quantum Cellular Automata
12%
Embedded Software
12%
Memory Architecture
12%
Built-in-self-test (BiST)
12%
Threshold Network
12%
Fault-tolerant Systems
12%
Distributed Architecture
11%
Fault Tolerance
11%
Synthesis System
11%
Security Protocols
11%
Memory-intensive Applications
11%
Systematic Codes
11%
Self-checking
11%
Multi-objective Genetic Algorithm
11%
Test Design
11%
Distributed Logic
11%
Partial Scan
11%
Robustness Testing
11%
Wearable Medical Devices
10%
Medical Devices
10%
Synthesis Algorithm
10%
Transistor Count
10%
Area Optimized
10%
Generation Framework
10%
Fault Diagnosis
10%
Custom Processors
10%
Fault Coverage
10%
System Specification
9%
Scheduling Algorithm
9%
Fault Tolerance System
9%
IPSec Protocol
9%
Trusted Platform Module
9%
Heterogeneous Distributed Embedded Systems
9%
Medical Body
9%
Schedule Length
9%
Single-chip System
9%
Multiprocessor Systems
9%
Client-server Systems
9%
Voltage Variation
9%
Separable Code
9%
System Synthesis
9%
IEEE Transactions
9%
Integrated Memories
9%
Stress Detection
9%
Stress Relief
9%
FinFET Circuits
9%
Leakage Power Analysis
9%
Low-cost Experiments
9%
Process Variation
9%
Static CMOS
9%
Machine Learning Ensemble
9%
Transform Network
9%
Engineering
Testability
62%
Logic Circuit
50%
Electric Power Utilization
49%
Energy Engineering
38%
Nodes
35%
Data Path
28%
Logic Gate
27%
Logic Synthesis
26%
Transients
26%
Process Variation
25%
Switch Voltage
24%
VLSI Circuits
24%
Fault Model
19%
Resonant Tunneling
18%
Power Management
18%
Control Signal
17%
Concurrent Error Detection
16%
Systematic Code
16%
Experimental Result
15%
Multiplexer
15%
Area Overhead
14%
Power Level
14%
Network-on-Chip
14%
Logic Design
14%
Test Level
14%
Control Flow
14%
Sequential Circuits
13%
Nanoscale
13%
Design Style
12%
Application Specific Integrated Circuit
12%
Test Sequence
12%
Level Model
12%
Tunnel Construction
12%
Single Electron
12%
Field Programmable Gate Arrays
12%
Applicability
11%
Regular Expression
11%
Boolean Logic
11%
Mixed Mode
11%
Field Effect Transistor
11%
Moore's Law
11%
Optimised Design
11%
Metrics
10%
Power Estimation
10%
Dynamic Reconfiguration
10%
Energy Systems
10%
Boolean Function
10%
Data Flow
10%
Circuit Design
10%
Level Energy
9%
Detecting Code
9%
Switching Activity
9%
Integrated Circuit
9%
Material Characteristic
9%
Deep Neural Network
9%
Gate Circuit
9%
Fits and Tolerances
9%
Adaptive Design
9%
Input Space
9%
Nanoelectronics
9%
Response Surface Methodology
9%
Information Symbol
9%
Generation Technology
9%
Optimization Technique
8%
Chip Area
8%
Symbolics
8%
Main Purpose
8%
Gate Length
8%
Interconnects
8%
High Level Synthesis
8%
Supply Voltage
8%
Microprocessor Chips
8%
Fine Grain
8%
Realization
8%
Design Space
7%
Voltage Scaling
7%
Core Loss
7%
Output Vector
7%
Compressive Sensing
7%
Three Dimensional Integrated Circuits
7%
Input Image
7%
Random Access Memory
7%
Nanowires
7%
Macromodel
7%
Limitations
7%
And Logic Gate
6%
Tasks
6%
Nanometre
6%
Built-in Self Test
6%
Long Short-Term Memory
6%
Reliability Availability and Maintainability (Reliability Engineering)
6%
Delay Constraint
6%
Hazards
6%
Sampled Signal
6%
Multiprocessor System
6%
Fin Thickness
6%
Bridging
5%
Data Signal
5%
Field-Effect Transistor
5%
Defects
5%
