Projects per year
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Dive into the research topics where David Wentzlaff is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
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Collaborations and top research areas from the last five years
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Projects
- 9 Finished
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SPX: Collaborative Research: Rethinking Data Center Abstractions Utilizing Warehouse-Scale Shared Memory
NSF - National Science Foundation
10/1/18 → 9/30/23
Project: Research project
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CRI: CI-New: OpenPiton 2: Enabling Open Source Manycore Hardware Research
NSF - National Science Foundation
6/15/18 → 5/31/23
Project: Research project
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Student Travel Support for the 50th IEEE/ACM Symposium on Microarchitecture (MICRO)
NSF - National Science Foundation
8/1/17 → 7/31/18
Project: Research project
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CAREER: Commonality Exploiting Architectures for Energy Efficiency
NSF - National Science Foundation
2/1/15 → 1/31/21
Project: Research project
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Looking Beyond the Dark, Rethinking General Purpose Computer Architecture for UAV and Space Processing
Space and Naval Warfare Systems Command
9/4/14 → 9/3/17
Project: Research project
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CIFER: A Cache-Coherent 12-nm 16-mm2SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm2Synthesizable eFPGA
Li, A., Chang, T. J., Gao, F., Ta, T., Tziantzioulis, G., Ou, Y., Wang, M., Tu, J., Xu, K., Jackson, P., Ning, A., Chirkov, G., Orenes-Vera, M., Agwa, S., Yan, X., Tang, E., Balkind, J., Batten, C. & Wentzlaff, D., 2023, In: IEEE Solid-State Circuits Letters. 6, p. 229-232 4 p.Research output: Contribution to journal › Article › peer-review
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CIFER: A 12nm, 16mm2, 22-Core SoC with a 1541 LUT6/mm21.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA
Chang, T. J., Li, A., Gao, F., Ta, T., Tziantzioulis, G., Ou, Y., Wang, M., Tu, J., Xu, K., Jackson, P. J., Ning, A., Chirkov, G., Orenes-Vera, M., Agwa, S., Yan, X., Tang, E., Balkind, J., Batten, C. & Wentzlaff, D., 2023, 2023 IEEE Custom Integrated Circuits Conference, CICC 2023 - Proceedings. Institute of Electrical and Electronics Engineers Inc., (Proceedings of the Custom Integrated Circuits Conference; vol. 2023-April).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
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Dalorex: A Data-Local Program Execution and Architecture for Memory-bound Applications
Orenes-Vera, M., Tureci, E., Wentzlaff, D. & Martonosi, M., 2023, 2023 IEEE International Symposium on High-Performance Computer Architecture, HPCA 2023 - Proceedings. IEEE Computer Society, p. 718-730 13 p. (Proceedings - International Symposium on High-Performance Computer Architecture; vol. 2023-February).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
3 Scopus citations -
DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET
Gao, F., Chang, T. J., Li, A., Orenes-Vera, M., Giri, D., Jackson, P. J., Ning, A., Tziantzioulis, G., Zuckerman, J., Tu, J., Xu, K., Chirkov, G., Tombesi, G., Balkind, J., Martonosi, M. R., Carloni, L. & Wentzlaff, D., 2023, 2023 IEEE Custom Integrated Circuits Conference, CICC 2023 - Proceedings. Institute of Electrical and Electronics Engineers Inc., (Proceedings of the Custom Integrated Circuits Conference; vol. 2023-April).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
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Duet: Creating Harmony between Processors and Embedded FPGAs
Li, A., Ning, A. & Wentzlaff, D., 2023, 2023 IEEE International Symposium on High-Performance Computer Architecture, HPCA 2023 - Proceedings. IEEE Computer Society, p. 745-758 14 p. (Proceedings - International Symposium on High-Performance Computer Architecture; vol. 2023-February).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
2 Scopus citations