Projects per year
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Dive into the research topics where Aarti Gupta is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
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Collaborative Research: SHF: Medium: Automated Word Level Synthesis for Hardware Code Generation and Verified Abstraction
NSF - National Science Foundation
7/15/21 → 6/30/24
Project: Research project
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FMitF: OpenRDC: A Framework for Implementing Open, Reliable, Distributed, Network Control
NSF - National Science Foundation
10/1/18 → 9/30/22
Project: Research project
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Verification Mentoring Workshop II
NSF - National Science Foundation
4/1/16 → 3/31/18
Project: Research project
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SHF: Small: Driving Learning for Program Verification
NSF - National Science Foundation
9/1/15 → 8/31/19
Project: Research project
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Verification Mentoring Workshop
NSF - National Science Foundation
4/1/15 → 3/31/16
Project: Research project
Research output
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Automatic Generation of Architecture-Level Models from RTL Designs for Processors and Accelerators
Zeng, Y., Gupta, A. & Malik, S., 2022, Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022. Bolchini, C., Verbauwhede, I. & Vatajelu, I. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 460-465 6 p. (Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
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Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models
Xing, Y., Gupta, A. & Malik, S., 2022, ASP-DAC 2022 - 27th Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 154-159 6 p. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2022-January).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
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Generating Architecture-Level Abstractions from RTL Designs for Processors and Accelerators Part I: Determining Architectural State Variables
Zeng, Y., Huang, B. Y., Zhang, H., Gupta, A. & Malik, S., 2021, 2021 40th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc., (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD; vol. 2021-November).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
1 Scopus citations -
Leveraging Processor Modeling and Verification for General Hardware Modules
Xing, Y., Lu, H., Gupta, A. & Malik, S., Feb 1 2021, Proceedings of the 2021 Design, Automation and Test in Europe, DATE 2021. Institute of Electrical and Electronics Engineers Inc., p. 1130-1135 6 p. 9474194. (Proceedings -Design, Automation and Test in Europe, DATE; vol. 2021-February).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
1 Scopus citations -
Pono: A Flexible and Extensible SMT-Based Model Checker
Mann, M., Irfan, A., Lonsing, F., Yang, Y., Zhang, H., Brown, K., Gupta, A. & Barrett, C., 2021, Computer Aided Verification - 33rd International Conference, CAV 2021, Proceedings. Silva, A. & Leino, K. R. (eds.). Springer Science and Business Media Deutschland GmbH, p. 461-474 14 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 12760 LNCS).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Open Access2 Scopus citations